1. Field of the Invention
This invention is related to the field of integrated circuit packaging and, more particularly to stackable integrated circuit packaging.
2. Description
Over the course of the development of the electronics industry, there has been an endless effort to increase both compactness and the performance of electronics products. The semiconductor devices have increased in terms of the numbers of transistors that can be created in a given space and volume, but it is the semiconductor package that has largely established the lower limits of the size of devices. So called chip scale and chip size packages have served well to meet this challenge by creating input/output (I/O) patterns for interconnection to the next level circuits, which are kept within the perimeter of the die. While this is suitable for making interconnection at near chip size, desire for even greater functionality in the same foot print and area has lead in recent years to increased interest in and to the development of stacked integrated circuit (IC) devices and stacked package assemblies. One area of specific interest and need is in the area of stacked chip assemblies for memory die. Particularly, the cost effectiveness of such solutions is of interest.
Crowley, et al. in U.S. Pat. No. 7,045,396 disclose a lead frame package that is stackable. Moreover, it discloses the use of a paddle which adds to package thickness and increases the package cross section profile. This is not suitable for applications wherein height standards must be met while stacking larger numbers of die (for example an eight high package stack), while still allowing for sufficient airflow between assemblies for cooling. Another example of a stackable lead frame package is described by Haba in United States Patent Application 2006/0118933 titled: “Stackable frames for packaging microelectronic devices”. Again the structure is not suitable for low profile stacking.
Huang discloses in U.S. Pat. No. 6,630,729 another approach to creating a stacked lead frame structure wherein the thickness of the lead frame establishes the thickness of the assembly and the lead frame is stacked.
Chye, et al in U.S. Pat. No. 6,951,982 disclose another approach to for a two stack lead frame integrated circuit (IC) package wherein the lower package has long leads and the upper package has short leads for connecting to the upper surface of the longer leads of the lower lead frame package.
Fee, et al. in U.S. Pat. No. 6,943,450 also disclose a stackable lead frame IC package.
Lyu, et al. in U.S. Pat. No. 6,878,570 disclose a method for stack assembly of lead frame packages.
Beyond the desire to provide for stacking, a feature for lead frame packages having small I/O terminals is that they have a design element such as lead features which allow for reliable capture of the lead in the resin and which will prevent the inadvertent removal of the leads from the encapsulant. An example of such is the rivet like contact is described in U.S. Pat. No. 6,001,671.
Methods used in the fabrication of lead frame packages having small terminals are known by those skilled in the art. For example, typical four sided flat or two sided flat type semiconductor packages, such as bottom lead type (e.g. quad flat no-lead (QFN)) or lead end grid array type semiconductor packages, can be fabricated using a method which may involve, for example, a sawing step for cutting up a semiconductor wafer having a plurality of semiconductor ICs into individual die. This is followed by a semiconductor die mounting step where the semiconductor die is joined to the paddles of lead frame die site and integrally formed on to the lead frame strip by means of a thermally-conductive adhesive resin. This step is followed by a wire bonding step where the innermost ends of the lead frame (i.e. closest to the die) are electrically connected to an associated I/O terminal of the semiconductor die. Next a resin encapsulation or molding step is performed to encapsulate each semiconductor die assembly including bonding wires for the semiconductor die and lead frame assembly. Next is a singulation step where the I/O leads and paddle connections of each lead frame unit are cut proximate to the lead frame to separate the semiconductor package assemblies from one another. These separated devices can be marked, tested and burned in to assure their quality. Depending on the lead frame design, the leads may be formed into a so-called “J-lead” or “gull wing” configuration. However when fabricating a bottom lead type or short peripherally leaded type semiconductor packages, the lead forming step is omitted. Instead, the lower surface or free end of each lead is exposed at the bottom of the encapsulation and the exposed portion of each lead may be used as an external I/O terminal for use with a socket or for attachment to a PCB with joining material such as a tin alloy solder. A semiconductor package structure created by the process just described can be seen in FIG. 1.
FIG. 1 also identifies the most basic elements of such a semiconductor IC package. The semiconductor IC package 100 includes a semiconductor die 101 bonded to a paddle 102 by means of a thermally-conductive epoxy resin 103 and a plurality of I/O leads 104 are arranged at each of either two or four sides of the paddle. The arrangement of the leads is laid out such that the leads are spaced apart from the side of the paddle while extending perpendicularly to the associated side of the paddle. The semiconductor package also includes a plurality of conductive wires 105 for electrically connecting the inner lead bond locations 107 to the semiconductor die bond sites 106, respectively, and a resin encapsulate 108 for encapsulating the semiconductor die and conductive wires. The semiconductor package further includes outer leads extending outwardly from the inner lead bond locations, respectively. The outer leads may have a particular shape such as a “J-lead” shape or a planar bottom lead shape, as shown. These outer leads serve to make interconnection to the next level assembly such as a PCB.
FIGS. 2 A-D shows various lead frame package configurations specifically designed for stacking or slightly modified to allow for stacking. FIG. 2A shows an example of a lead frame with a J or C shape allowing soldering from one lead to the other in the same foot print. FIG. 2B shows an example of a straight lead semiconductor package in stacked form. The leads could also be shaped in a “gull wing” form if desired. FIG. 2C shows another example of a lead frame structure where the lead frame is accessed from top and bottom at offset points. This allows for stacking at lower profile, however the foot print is different on the two sides. FIG. 2D shows yet another stacking structure.
FIGS. 3A-3C show example solutions for stacking semiconductor die themselves rather than stacking the assembled packages. Often there is a preparatory step involving the creation of a redistribution circuit layer (RDL), especially in the cases where the die terminations are in the center, such as DRAM die. The RDL is a layer of circuits which interconnect native and primary semiconductor die I/O terminals to secondary I/O terminal locations distal from the original I/O locations.
FIG. 3A shows an example of such a stacked die assembly 300A construction where the central I/O terminals of the die 301 have been redistributed to the edge 302 using a redistribution circuit 303. A connection to each of the die is made at the edge contact using a conductive material 304. Such assemblies could be mounted directly on to PCBs, however they would very difficult to standardize.
FIG. 3B shows a stack die assembly construction 300B designed to overcome this limitation by assembling the stacked die on an interposer 305 to make possible interconnection to a standard registered outline, such as those published by JEDEC (Joint Electronic Device Council a division of the American Electronics Association).
FIG. 3C shows another example of a stacked die assembly package 300C where the semiconductor die 306 are interconnected to a common base substrate 307 by means of wire bonds 308. The semiconductor dice are separated by spacers 309, which add height to prevent the wires from touching the die above. The stacked semiconductor die are assembled on an interposer having a standard or registered I/O footprint or one that can be easily registered or made standard.
FIGS. 4A and 4B show additional stacked semiconductor die packaging solutions wherein the semiconductor die are stacked into an assembly and interconnected to one another through holes filled with a conductive material. This allows interconnections to be made through the silicon (or other base semiconductor material). For practical reasons, the semiconductor die are commonly stacked in wafer form. This approach, however, increases the probability that there may be a bad die in some quantity of the final stacked die assemblies. Even with high yields, the factorial effect can have a significant impact on overall assembly yield. (E.g., with 98% yield per wafer, the maximum statistical yield is 83% for an 8 high stack).
FIG. 4A shows an example of such an assembly 400A with metal filled conductive vias 401 making interconnection from one die to the next through each semiconductor die from top to bottom. On one (or possibly both) surfaces the I/O are redistributed over the surface of the die face to facilitate assembly at the next interconnection level such as a module or PCB.
FIG. 4B shows another example of such a stacked die assembly with interconnections made from die to die using metal filled conductive vias. The stacked semiconductor die assembly is shown mounted onto an interposer 402 which can have a standard or registered I/O footprint or an I/O footprint that can be easily registered or made standard.
A difficulty for stacked die semiconductor package constructions is that burn in of the bare die is difficult and such die if available can be expensive. Another reason is that semiconductor die of different generations and/or from different suppliers will normally be of slightly different size and shape and often have slightly different I/O layout. Another concern for any stacked die semiconductor package solution, which does not employ known good die, is that the assembly yield is not knowable until the final assembly is tested and burned in. This is a potentially costly proposition.
While the invention is susceptible to various modifications and alternative forms, specific embodiments thereof are shown by way of example in the drawings and will herein be described in detail. It should be understood, however, that the drawings and detailed description thereto are not intended to limit the invention to the particular form disclosed, but on the contrary, the intention is to cover all modifications, equivalents and alternatives falling within the spirit and scope of the present invention as defined by the appended claims.